Tests on a variety of devices, e.g. with an IC tester, and tests of electronic circuits with waveform generators, often require generation of a timing edge that is not limited to the period of a clock which becomes a basis of the system (i.e., a master clock (MCLK)). FIG. 5 shows a conventional timing edge generation circuit used in IC testers. The MCLK feeds a constant high frequency (for instance, 100 MHz to 500 MHz) to the timing edge generator. The period clock (PCLK) determines a test cycle and is preferably a certain multiple of the master-clock period.
The circuit of FIG. 5 includes a memory (time data RAM 1), a counter 2, a fine timing indication circuit (FIFO 3), a timing adjustment circuit (time vernier 4) and flip-flops 5, 6, and 7. The timing data (timing.sub.-- data) includes counter data (counter.sub.-- data) and vernier data (vernier.sub.-- data.sub.-- in) is stored in a time data RAM 1. The time data RAM 1 outputs predefined timing.sub.-- data each time an active edge of the PCLK is input to its strobe terminal.
The counter 2 receives counter.sub.-- data from the time data RAM 1 and includes a start selector 21, count circuits 221 through 224, and an OR gate 23. The start selector 21 selects sequentially count circuits 221-224 in response to "start" signal from FF 6 (one MCLK delayed signal from an output of FF 5). Count circuits 221-224 will count a number of cycles of the MCLK which is indicated by the counter.sub.-- data, when they receive a signal for starting to count from start selector 21, and then will provide digital delay signals DD.sub.-- m1 through the OR gate 23 at a timing corresponding to the count value. Digital delay signals DD.sub.-- m1 are digitally delayed "start" signal in accordance with the value of counter.sub.-- data.sub.-- in by counter 2.
"Fifo.sub.-- in" signals synchronized with MCLK are provided from FF 5 to an input indication terminal "in" of FIFO 3. FIFO 3 receives vernier.sub.-- data.sub.-- in upon a rising edge of fifo.sub.-- in. In turn, vernier.sub.-- data, which are stored in FIFO 3, are sequentially input to the time vernier 4 in a timing of an output edge of DD.sub.-- m1 from the counter 2 (output edge from respective count circuits 221-224). FF 7 provides DD.sub.-- m1 to the time vernier 4 as digital delay signals DD which is synchronized with MCLK. Time vernier 4 then delays DD in accordance with a content of vernier.sub.-- data and outputs fine edge signals FE.
FIGS. 6 through 8 illustrate a circuit of time vernier 4. In FIG. 6, a time vernier 4 is comprised of a digital-analog converter (DAC) 401, a ramp signal generation circuit 402, and a comparator 403. DAC 401 receives vernier.sub.-- data and converts it to an analog reference voltage (V.sub.dac). The ramp signal generation circuit 402 includes a switch (SW.sub.r), in which one of its terminals is grounded, and which will turn off in response to a rising edge of digital delay signals DD, a capacitor (C.sub.r) for ramp voltage generation and a current source (l.sub.r) which will charge C.sub.r when switch SW.sub.r is opened. The comparator 403 compares the charge voltage of C.sub.r (ramp voltage V.sub.ramp) and V.sub.dac, and outputs its result which will be referred as fine edge signals FE.
Charging of C.sub.r begins when SW.sub.r is opened by an edge input of the digital delay signals DD. When the charge voltage V.sub.ramp of C.sub.r is less than V.sub.dac, the output of FE is "0". When V.sub.ramp exceeds V.sub.dac, FE becomes "1". That is, the comparator 403 will output FE when the time corresponding to a value of V.sub.dac has elapsed.
A time vernier 4 in FIG. 7 comprises CMOS circuits 411 and 412, and a group of capacitors which is digitally adjustable of its capacity (shown as a variable capacitor C.sub.v). PCTRL is input to P-MOST.sub.1 and P-MOST.sub.2 gate terminals of both CMOS circuits. Digital delay signals DD are input to an input terminal (a gate terminal of N-MOST.sub.1) of CMOS circuit 411. One end of C.sub.v is connected to a low voltage power source, while the other end is connected between terminals of respective P-MOST and N-MOST of both CMOS circuits 411 and 412.
In the circuit shown in FIG. 7, when an edge is input to N-MOST.sub.1 gate, fine edge signals FE are output at an output which terminal of CMOS circuit 412 after a specific time, depends on the capacity of C.sub.v, being elapsed. However, there is a problem with timing adjustment circuits (time vernier 4) shown in FIGS. 6 and 7 in that both a sufficient timing adjustment range and a good resolution cannot be simultaneously accomplished, when either of these circuits is used exclusively.
A time vernier shown in FIG. 8 comprises fine delay means 420, coarse delay elements 421 through 427, calibrating registers for a calibration of these coarse delay elements (indicated by 428), and a multiplexer (MUX) 429 which selectively outputs signals p0 from fine delay means 420 and signals p1 through p7 that have been coarsely delayed by coarse delay elements 421-427. Data (vernier.sub.-- data.sub.-- 5), which is comprising (e.g. the least significant 5 bits) of total bits (8 bits in this figure) of vernier.sub.-- data, is input to the fine delay element 420, while data (vernier.sub.-- data.sub.-- 3), including remaining bits (the most significant 3 bits in the figure) is input to the multiplexer 429. When the digital delay signals DD has been finely delayed in accordance with the value of aforementioned vernier.sub.-- data.sub.-- 5 by fine delay means 420, it is coarsely delayed in sequence by coarse delay elements 421-427. The multiplexer 429 selects one signal from p0 through p7 in accordance with the value of vernier.sub.-- data.sub.-- 3 and outputs this as fine edge signals FE.
Assuming that the amount of a delay time by each coarse delay means 421-427 is .tau..sub.d, when the delay time amount of fine delay element 420 is less than .tau..sub.d, there will be an amount in which such delay time cannot be set. Therefore, a delay time amount that is equal or greater than .tau..sub.d is generally used for fine delay means 420.
The operation of the timing edge generation circuit in FIG. 5, which uses the circuit of FIG. 8 as timer vernier 4, will now be explained. The PCLK is provided to a timing edge generation circuit during a period that is two times of the period T of MCLK. As previously mentioned, when the rising edge of the PCLK is input to the strobe terminal of time data RAM 1, time data RAM 1 outputs timing.sub.-- data. Then, vernier.sub.-- data.sub.-- in (8 bits in the example in FIG. 5) are output to FIFO 3, and counter.sub.-- data (8 bits in the example in FIG. 5) are output to counter 2. Now, the PCLK is continuously input over 3 clocks to the aforementioned timing edge generation circuit and following data are output in sequence from the time data RAM 1 (the numbers in parentheses indicate an output sequence from the time data RAM 1).
timing.sub.-- data(1) PA1 timing.sub.-- data(2) PA1 timing.sub.-- data(3) PA1 timing.sub.-- data(1) PA1 timing.sub.-- data(2) PA1 timing.sub.-- data(3) PA1 timing.sub.-- data(4)
counter.sub.-- data(1):00000001 PA2 vernier.sub.-- data(1):01111110 PA2 counter.sub.-- data(2):00000010 PA2 vernier.sub.-- data(2):10111110 PA2 counter.sub.-- data(3):00000011 PA2 vernier.sub.-- data(3):11011100 PA2 counter.sub.-- data(1):00000000 PA2 vernier.sub.-- data(1):01111110 PA2 counter.sub.-- data(2):00000000 PA2 vernier.sub.-- data(2):10111110 PA2 counter.sub.-- data(3):00000000 PA2 vernier.sub.-- data(3):11011100 PA2 counter.sub.-- data(4):00000000 PA2 vernier.sub.-- data(4):00000000
In this case, when "start" signals are input, count circuits 221-224 in FIG. 5 output digital delay signals DD.sub.-- m1 after counting a specific number of MCLK, which corresponds to the value of respective counter.sub.-- data (as shown in FIG. 9). In FIG. 9, the number of MCLK to be counted during from the rising of "start" signals until an input of DD.sub.-- m1 are shown by reference numbers in circles.
As explained with FIG. 8, after digital delay signals DD are finely delayed by the fine delay circuit 420 (in accordance with vernier.sub.-- data.sub.-- 5), it will be coarsely delayed by coarse delay circuits 421-427. Multiplexer 429 in turn selects any of the aforementioned signals p0 through p7 and outputs these selected signals as fine edge signals FE in accordance with vernier.sub.-- data.sub.-- 3. In the example shown in FIG. 9, vernier.sub.-- data.sub.-- 3 is 011, 101 and 110, and signals p3, p5 and p6 are sequentially selected and output FE. A correct FE is obtained since DD signals are separated by 2 MCLK periods in time sequence. However, if DD signals are separated by less than 2 MCLK periods, following problems occurred.
When DD signals are propagated while it is delayed by delay elements 421-427, time vernier 4, which originally must operate in accordance with vernier data (n) (n is an integer), will operate in accordance with new vernier.sub.-- data(n+1) when next DD.sub.-- m1 is newly input to an output terminal of FIFO 3. Therefore, (i) glitches accompanying a change of the vernier.sub.-- data may be appeared, and (ii) when an edge is output from an delay element, previous vernier.sub.-- data(n) is renewed with new vernier.sub.-- data(n +1) and therefore, delay element can not provide the output to be originally selected.
FIG. 10 shows a timing chart when PCLK is continuously input over 4 clocks to the aforementioned timing edge generation circuit, and vernier.sub.-- data with counter.sub.-- data of 00000000 is output as shown below from time data RAM 1.
FIG. 10 illustrates cases where glitches are appeared in fine edge signals FE (A.sub.1, A.sub.2) and where there is no output (A.sub.3). {P In order to solve such problems, conventionally the method is also known whereby, as shown in FIG. 11, by using several vernier circuits (4a through 4d) digital delay signals DD, which is continuously input, is delayed in sequence by vernier circuits 4a-4d and output through OR gate 430. However, the cost of the timing edge generation circuit or an apparatus including such generation circuit becomes high since an delay element is expensive and also following problems tend to occur.
Even if finely adjusted, the timing generated by four different vernier circuits 4a-4d may be offset to the extent of 10 to 50 ps (position of the edges from vernier circuits 4a-4d may fluctuate by, for instance, 10 to 50 ps). Consequently, the edge timing of fine edge signals FE includes an error component that is periodically fluctuated, in which this period may be four period of DD. By monitoring fine edge signals FE by a spectrum analyzer, in addition to a basic wavelength (basic wave of a waveform where its period is four periods of DD), 1/2 and 1/4 frequency components can be detected.
When this type of fine edge signal FE is used as a conversion clock for a digital-analog converter or an analog-digital converter, such fluctuation in timing may be converted to an error in amplitude, and the measurement result therefore includes a periodic error (error during a period of four periods of DD may be appeared). For example, in a spectrum analyzer timing edge generation circuit such as shown in FIG. 11 is used, a periodic error may be appeared as an excess spectrum, an accuracy of the measurement may be deteriorated.